Technical Q&A's

HW 05 - PCI Bus Performance with Memory Read and Memory Read Multiple Commands (15-July-95)

Q If I attempt to transfer a full cache line using the Memory Read command, will I get lower performance than if I make the same transfer with the Memory Read Multiple command?

A Yes. If you use Memory Read instead of Memory Read Line or Memory Read Multiple, you will be disconnected at eight byte boundaries, because, just as with the writes, that is the size of a PowerPC single transaction. In the first implementation, a Memory Read Line and Memory Read Multiple are dealt with in the same way. There is no optimization for Memory Read Multiple. However, you should use the Memory Read Multiple transaction if that is what your PCI Master is doing, i.e., transferring multiple cache lines. Future bridges should take advantage of that. If you are doing a cache line read, or even close to a full cache line, you should do a Memory Read line.

Follow the PCI Specification's description of the different cycles. The general rule of thumb is:

* If the number of data phases is <= 2, use Memory Read.

* If the number of data phases is > 2 and <= the cache line size, use Memory Read Line.

* If the number of data phases > one cache line, use Memory Read Multiple.

There are better guidelines than these in Rev. 2.1 of the PCI Specification. Although the PCI SIG hasn't officially released this revision of the specification, it should be available from your company's PCI SIG representative.

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